As device dimensions in integrated circuits continue to decrease, planarization of topographical features becomes more critical. When exposing a pattern using photolithography, large differences in step height across the exposed area will cause some of the pattern to be out of focus. This effect results from the limited depth of focus available with existing photolithography technology. The problem is most serious for devices smaller than 1 micron. Existing technology normally can maintain a good depth of focus between plus or minus 0.3 microns. When portions of the exposed areas are out of focus, metal leads may be open or the "via holes" may not open up uniformly.
For submicron-sized devices, therefore, it is desirable to planarize topographical features before fabricating a subsequent patterned layer. Engineers have proposed two principle methods for achieving global planarization: chem-mechanical polishing and patterned resist etchback. In chem-mechanical polishing, a slurry film etches a wafer while a pad is used to apply mechanical pressure and increase the etch rate. Areas on the wafer that are "higher" on the surface are etched more quickly. Unfortunately, chem-mechanical polishing does not give ideal global planarization. Instead, this process causes pattern density effects which are more significant as die sizes increase.
Patterned resist etchback involves globally planarizing a structure after a patterned layer has been formed and an oxide or dielectric layer has been deposited on top of the patterned level. The oxide layer tends to be raised in the vicinity of structures on the patterned layer and tends to have valleys where there is no structure on the patterned layer. The patterned resist etchback process planarizes the oxide level.
The first step in the patterned resist etchback process is to deposit a reverse pattern of the patterned layer on top of the oxide. This layer, known as the planarizing block layer, can be formed using a negative of the mask used to form the patterned layer. After the reverse pattern has been deposited, the resulting layer comprises structures that fill the valleys of the oxide layer. Next, a layer of photoresist is spun on, thus providing a substantially planarized surface. The substantially planarized surface is then etched using a process that will etch the photoresist and oxide at the same rate, thus producing a planarized oxide surface. After the oxide has been planarized, additional patterned layers may be deposited on top of the oxide layer.
Although patterned resist etchback is a good method to achieve global planarization, it adds a significant number of processing steps as one must perform the method after forming each patterned level. These additional processing steps also increase the amount of chemicals needed to fabricate an integrated circuit. As a result, patterned resist etchback causes both the cost and time of production to increase.